CVE-2023-44297
Dell Poweredge R660 Firmware 1.4.4
Raw vector
CVSS:3.1/AV:P/AC:H/PR:N/UI:N/S:C/C:H/I:H/A:LCVSS and EPSS are reproduced from their sources (NVD, FIRST EPSS). Risk Priority is our own derived reading, not an NVD score.
Summary
CVE-2023-44297 is a high-severity Hardware Internal or Debug Modes Allow Override of Locks (CWE-1234) vulnerability in Dell Poweredge R660 Firmware. Its CVSS base score is 7.1 (High).
Operationally, exploitation aligns with the MITRE ATT&CK technique Data Obfuscation (T1001); ranked at the 16th percentile by exploit likelihood (below the median); it is not currently listed in the CISA KEV catalog.
EU & UK References
- 🇪🇺 ENISA EUVD: EUVD-2023-48653
Vulnerability Data
Dell PowerEdge platforms 16G Intel E5 BIOS and Dell Precision BIOS, version 1.4.4, contain active debug code security vulnerability. An unauthenticated physical attacker could potentially exploit this vulnerability, leading to information disclosure, information tampering, code execution, denial of service.
- CWE(s)
Related Threats
MITRE ATT&CK Enterprise Techniques
CVEs Like This One
Affected Assets
Mitigating Controls
Mitigating Controls (NIST CSF 2.0) AI
Derived directly from the weakness types (CWEs) cited in the NVD entry via our AI-authored CWE→CSF cross-walk (authority under review) — links open the control.
Identifying hardware vulnerabilities can surface debug-mode bypass risks before deployment.
Hardware integrity assessment prior to acquisition directly evaluates secure debug/lock behavior.
Hardened configuration baselines can disable or lock debug modes in production hardware.
Hardware replacement decisions can address devices lacking proper debug-lock protections.
Mitigating Controls (ISO/IEC 27001:2022 Annex A) AI
Derived directly from the weakness types (CWEs) cited in the NVD entry via our AI-authored CWE→ISO cross-walk (authority under review) — links open the control.
Restricting privileged utility programs limits debug access, but does not guarantee hardware lock protection.
Privileged access rights can restrict debug-mode overrides but do not specifically address hardware lock bypass.
Secure development lifecycle includes concurrency and locking requirements that reduce improper locking defects.
Secure system architecture and engineering principles can mandate hardware lock enforcement during debug, covering most of the weakness.
Hardening callouts derived
DISA STIG baselines are authored against specific weaknesses. Where this CVE cites a broad weakness class, the mapping is not asserted at that abstraction (owner ruling, 2026-09-25: grade only at Base and below), so no rule is shown here rather than a rule shown against the wrong grain.
- No fine-grained STIG row for CWE-667, a class-level weakness, and none of its children carries one either.