Security Resilience

CVE-2024-21853

Published
13 November 2024
Modified
15 April 2026
CVSS Score v4 5.7
Click a component to see what it means
Raw vectorCVSS:4.0/AV:L/AC:H/AT:N/PR:L/UI:N/VC:N/VI:N/VA:H/SC:N/SI:N/SA:N/E:X/CR:X/IR:X/AR:X/MAV:X/MAC:X/MAT:X/MPR:X/MUI:X/MVC:X/MVI:X/MVA:X/MSC:X/MSI:X/MSA:X/S:X/AU:X/R:X/V:X/RE:X/U:X
EPSS Score 0.0023 12th percentile
Risk Priority 23 floored blend · peak EPSS

CVSS and EPSS are reproduced from their sources (NVD, FIRST EPSS). Risk Priority is our own derived reading, not an NVD score.

Summary

CVE-2024-21853 is a medium-severity Improper Finite State Machines (FSMs) in Hardware Logic (CWE-1245) vulnerability in Intel (inferred from references). Its CVSS base score is 5.7 (Medium).

Operationally, exploitation aligns with the MITRE ATT&CK technique Junk Data (T1001.001); ranked at the 12th percentile by exploit likelihood (below the median); it is not currently listed in the CISA KEV catalog.

The strongest mitigations our analysis identified map to SA-11 (Developer Testing and Evaluation) and SC-24 (Fail in Known State) — see the control section below for these in your framework.

EU & UK References

Vulnerability Data

Improper finite state machines (FSMs) in the hardware logic in some 4th and 5th Generation Intel(R) Xeon(R) Processors may allow an authorized user to potentially enable denial of service via local access.

CWE(s)
CWE-1245

Related Threats

MITRE ATT&CK Enterprise Techniques

T1001.001 Junk Data Command And Control
Adversaries may add junk data to protocols used for command and control to make detection more difficult.
attack.mitre.org →
T1001.002 Steganography Command And Control
Adversaries may use steganographic techniques to hide command and control traffic to make detection efforts more difficult.
attack.mitre.org →
T1003.002 Security Account Manager Credential Access
Adversaries may attempt to extract credential material from the Security Account Manager (SAM) database either through in-memory techniques or through the Windows Registry where the SAM database is stored.
attack.mitre.org →
T1003.005 Cached Domain Credentials Credential Access
Adversaries may attempt to access cached domain credentials used to allow authentication to occur in the event a domain controller is unavailable.
attack.mitre.org →
T1003.007 Proc Filesystem Credential Access
Adversaries may gather credentials from the proc filesystem or `/proc`.
attack.mitre.org →
T1003.008 /etc/passwd and /etc/shadow Credential Access
Adversaries may attempt to dump the contents of <code>/etc/passwd</code> and <code>/etc/shadow</code> to enable offline password cracking.
attack.mitre.org →
Derived from this CVE’s CWE(s) via the direct CWE→ATT&CK cross-walk.

CVEs Like This One

CVE-2024-31068Shared CWE-1245
CVE-2024-58311Shared CWE-1245
CVE-2025-48508Shared CWE-1245
CVE-2024-24968Shared CWE-1245

Affected Assets

Intel
—
inferred from references and description; NVD did not file a CPE for this CVE

Mitigating Controls

Mitigating Controls (NIST 800-53 r5) AI

SA-11 Developer Testing and Evaluation good match

Developer testing and evaluation at post-design stages can discover undefined or insecure FSM states through simulation and formal verification.

SC-24 Fail in Known State good match

Forcing a transition to a known safe state on failure limits the impact of an attacker-driven undefined FSM state.

SA-17 Developer Security and Privacy Architecture and Design partial match

Requiring the developer to produce a security architecture and design description forces explicit FSM modeling and review before implementation.

SA-8 Security and Privacy Engineering Principles partial match

Security engineering principles applied during hardware design directly reduce the chance of introducing faulty FSM transitions or unreachable states.

Mitigating Controls (NIST CSF 2.0) AI

Derived directly from the weakness types (CWEs) cited in the NVD entry via our AI-authored CWE→CSF cross-walk (authority under review) — links open the control.

PR.PS-06 partial match
blocks

Secure development practices and verification throughout the lifecycle directly prevent faulty FSM implementations in hardware logic.

Mitigating Controls (ISO/IEC 27001:2022 Annex A) AI

Derived directly from the weakness types (CWEs) cited in the NVD entry via our AI-authored CWE→ISO cross-walk (authority under review) — links open the control.

A.5.2 Information security roles and responsibilities partial match
removes
A.8.25 Secure development life cycle partial match
blocks

Secure development lifecycle includes hardware design reviews that can catch FSM flaws.

A.8.26 Application security requirements partial match
removes
A.8.27 Secure system architecture and engineering principles partial match
blocks

A.8.27 mandates security-by-design, defense-in-depth, least privilege, fail-secure, and security-oriented design reviews that can catch and block many FSM transition errors before they reach silicon, but leaves a bounded remainder (undocumented states, timing/analog edge cases, and post-silicon FSMs) that the clause does not reach.

A.8.28 Secure coding partial match
prevents

Secure coding guidelines can extend to hardware description languages to prevent FSM coding errors.

A.8.29 Security testing in development and acceptance partial match
finds

Security testing in development can discover undefined FSM states before deployment.

References