CVE-2024-4231
Raw vector
CVSS:4.0/AV:P/AC:L/AT:N/PR:N/UI:N/VC:H/VI:H/VA:N/SC:N/SI:N/SA:N/E:X/CR:X/IR:X/AR:X/MAV:X/MAC:X/MAT:X/MPR:X/MUI:X/MVC:X/MVI:X/MVA:X/MSC:X/MSI:X/MSA:X/S:X/AU:X/R:X/V:X/RE:X/U:XSummary
CVE-2024-4231 is a medium-severity On-Chip Debug and Test Interface With Improper Access Control (CWE-1191) vulnerability. Its CVSS base score is 6.8 (Medium).
Operationally, exploitation aligns with the MITRE ATT&CK technique OS Credential Dumping (T1003); ranked at the 44th percentile by exploit likelihood (below the median); it is not currently listed in the CISA KEV catalog.
The strongest mitigations our analysis identified map to AC-3 (Access Enforcement) and AC-6 (Least Privilege) — see the control section below for these in your framework.
EU & UK References
- 🇪🇺 ENISA EUVD: EUVD-2024-32783
Vulnerability Data
This vulnerability exists in Digisol Router (DG-GR1321: Hardware version 3.7L; Firmware version : v3.2.02) due to presence of root terminal access on a serial interface without proper access control. An attacker with physical access could exploit this by identifying UART…
more
pins and accessing the root shell on the vulnerable system. Successful exploitation of this vulnerability could allow the attacker to access the sensitive information on the targeted system.
- CWE(s)
Related Threats
MITRE ATT&CK Enterprise Techniques
CVEs Like This One
Affected Assets
Mitigating Controls
Mitigating Controls (NIST 800-53 r5) AI
AC-3 directly requires enforcement of authorization checks on all logical access paths, which would block unauthorized use of the debug/test interface registers.
AC-6 requires restricting access rights to the minimum needed, limiting what an attacker reaching the debug interface can actually read or modify.
IA-3 requires device identification and authentication before any connection is established, which would apply to external debug or test equipment.
Mitigating Controls (NIST CSF 2.0) AI
Derived directly from the weakness types (CWEs) cited in the NVD entry via our AI-authored CWE→CSF cross-walk (authority under review) — links open the control.
Defining and enforcing access permissions directly addresses improper authorization to debug interfaces.
Managing physical access to assets covers control of on-chip debug/test ports and pins.
Authentication of hardware can help restrict debug interface use but is narrower than full access control.
Mitigating Controls (ISO/IEC 27001:2022 Annex A) AI
Derived directly from the weakness types (CWEs) cited in the NVD entry via our AI-authored CWE→ISO cross-walk (authority under review) — links open the control.
Security testing can discover improper debug access but does not itself implement the control.
Physical perimeters can limit access to debug ports but do not address on-chip access-control logic.
Physical entry controls reduce the chance of an attacker reaching the chip but do not enforce on-chip debug authorization.
Privileged-access rules may extend to hardware debug interfaces, yet the control is not hardware-specific.
Secure SDLC encourages hardware security requirements but does not mandate debug-port controls.
Secure architecture principles include hardware access-control mechanisms for debug and test interfaces.