CVE-2023-38420
Intel Power Gadget
Raw vector
CVSS:3.1/AV:L/AC:L/PR:L/UI:N/S:C/C:L/I:N/A:NCVSS and EPSS are reproduced from their sources (NVD, FIRST EPSS). Risk Priority is our own derived reading, not an NVD score.
Summary
CVE-2023-38420 is a low-severity Improper Check for Unusual or Exceptional Conditions (CWE-754) vulnerability in Intel Power Gadget. Its CVSS base score is 3.8 (Low).
Operationally, ranked at the 12th percentile by exploit likelihood (below the median); it is not currently listed in the CISA KEV catalog.
The strongest mitigations our analysis identified map to SA-11 (Developer Testing and Evaluation) and SC-24 (Fail in Known State) — see the control section below for these in your framework.
OWASP Top 10 for Web (2025)
EU & UK References
- 🇪🇺 ENISA EUVD: EUVD-2023-42237
Vulnerability Data
Improper conditions check in Intel(R) Power Gadget software for macOS all versions may allow an authenticated user to potentially enable information disclosure via local access.
- CWE(s)
Related Threats
CVEs Like This One
Affected Assets
Mitigating Controls
Mitigating Controls (NIST 800-53 r5) AI
Developer testing and evaluation explicitly exercises unusual conditions to find missing or incorrect checks.
Enforces failure to a known state while preserving required properties, limiting impact of unhandled exceptions.
Input validation directly requires checking for unexpected or malformed conditions before they propagate.
Mandates explicit fail-safe procedures triggered by indicated failures, structurally preventing unhandled exceptional conditions.
Security engineering principles include structured handling of edge cases and exceptions during design.
Requires generation of safe, actionable error messages that directly addresses proper handling of exceptional conditions.
Mitigating Controls (ISO/IEC 27001:2022 Annex A) AI
Derived directly from the weakness types (CWEs) cited in the NVD entry via our AI-authored CWE→ISO cross-walk (authority under review) — links open the control.
Logging can record unhandled exceptions but does not prevent the weakness itself.
Monitoring may detect symptoms of unhandled conditions but does not eliminate the root weakness.
Secure development life cycle mandates exception handling and input validation that directly prevent missing checks for unusual conditions.
Application security requirements explicitly call for handling of exceptional conditions and error paths.
A.8.27 mandates security-by-design principles (fail securely, least privilege, distrust external input, security-oriented design reviews) that reach some but not most CWE-754 cases; many exceptional-condition checks live in low-level code paths outside architecture-level engineering.
Secure coding standards directly mandate proper checks for exceptional and unusual conditions.
Hardening callouts derived
DISA STIG baselines are authored against specific weaknesses. Where this CVE cites a broad weakness class, the mapping is not asserted at that abstraction (owner ruling, 2026-09-25: grade only at Base and below), so no rule is shown here rather than a rule shown against the wrong grain.
- No fine-grained STIG row for CWE-754, a class-level weakness. Rules are authored against its narrower children: CWE-354.
- No fine-grained STIG row for CWE-703, a pillar-level weakness, and none of its children carries one either.