Security Resilience

CVE-2024-23599

Race Condition

Published
16 September 2024
Modified
15 April 2026
CVSS Score v4 8.3
Click a component to see what it means
Raw vectorCVSS:4.0/AV:L/AC:L/AT:N/PR:H/UI:N/VC:N/VI:H/VA:H/SC:N/SI:H/SA:H/E:X/CR:X/IR:X/AR:X/MAV:X/MAC:X/MAT:X/MPR:X/MUI:X/MVC:X/MVI:X/MVA:X/MSC:X/MSI:X/MSA:X/S:X/AU:X/R:X/V:X/RE:X/U:X
EPSS Score 0.0012 2th percentile
Risk Priority 25 floored blend · peak EPSS

CVSS and EPSS are reproduced from their sources (NVD, FIRST EPSS). Risk Priority is our own derived reading, not an NVD score.

Summary

CVE-2024-23599 is a high-severity Race Condition (CWE-362) vulnerability in Intel (inferred from references). Its CVSS base score is 8.3 (High).

Operationally, ranked at the 2th percentile by exploit likelihood (below the median); it is not currently listed in the CISA KEV catalog.

The strongest mitigations our analysis identified map to SC-39 (Process Isolation) and SC-4 (Information in Shared System Resources) — see the control section below for these in your framework.

OWASP Top 10 for Web (2025)

EU & UK References

Vulnerability Data

Race condition in Seamless Firmware Updates for some Intel(R) reference platforms may allow a privileged user to potentially enable denial of service via local access.

CWE(s)

Related Threats

CVEs Like This One

CVE-2025-38085Shared CWE-362
CVE-2024-47741Shared CWE-362
CVE-2026-50450Shared CWE-362
CVE-2025-23259Shared CWE-362
CVE-2025-71066Shared CWE-362
CVE-2025-39726Shared CWE-362
CVE-2026-26074Shared CWE-362
CVE-2024-32908Shared CWE-362
CVE-2026-63971Shared CWE-362
CVE-2025-47972Shared CWE-362

Affected Assets

Intel
—
inferred from references and description; NVD did not file a CPE for this CVE

Mitigating Controls

Mitigating Controls (NIST 800-53 r5) AI

Maintaining separate execution domains for each process structurally eliminates unintended concurrent access to the same shared resources.

Preventing unintended information transfer through shared system resources directly addresses the improper concurrent modification that defines a race condition.

Mitigating Controls (ISO/IEC 27001:2022 Annex A) AI

Derived directly from the weakness types (CWEs) cited in the NVD entry via our AI-authored CWE→ISO cross-walk (authority under review) — links open the control.

blocks

A.8.25 mandates secure SDLC practices (secure coding guidelines, security requirements, checkpoints, testing including code scans/penetration tests, developer training) that reach race conditions in concurrent code, but only as one slice of a broad requirement whose implementation scope and rigour are left to the organisation.

blocks

A.8.26 explicitly lists resilience against malicious attacks including SQL injections and input validation as application security requirements to identify/address; race conditions are a similar class of timing-based concurrency flaw that can be mitigated by requirements for proper synchronization/locking, but this is only one slice of the broad CWE-362 class (most instances arise in low-level shared-memory or TOCTOU scenarios not named here).

blocks

Secure architecture principles require proper synchronization and resource isolation, addressing the root cause of CWE-362.

prevents

Secure coding standards explicitly forbid unsafe concurrent access patterns and mandate atomic operations or locks.

finds

Security testing can detect race conditions, but does not prevent them at design or coding time.

Hardening callouts derived

DISA STIG baselines are authored against specific weaknesses. Where this CVE cites a broad weakness class, the mapping is not asserted at that abstraction (owner ruling, 2026-09-25: grade only at Base and below), so no rule is shown here rather than a rule shown against the wrong grain.

  • No fine-grained STIG row for CWE-362, a class-level weakness, and none of its children carries one either.

References