Cyber Resilience

CVE-2026-29643

Published
20 April 2026
Modified
21 April 2026
CVSS Score v3.1 7.1
Click a component to see what it means
Raw vectorCVSS:3.1/AV:L/AC:L/PR:L/UI:N/S:U/C:N/I:H/A:H
EPSS Score 0.0016 6th percentile
Risk Priority 50 floored blend · peak EPSS

Summary

CVE-2026-29643 is a high-severity Improper Check or Handling of Exceptional Conditions (CWE-703) vulnerability in Riscv (inferred from references). Its CVSS base score is 7.1 (High).

Operationally, exploitation aligns with the MITRE ATT&CK technique Endpoint Denial of Service (T1499); ranked at the 6th percentile by exploit likelihood (below the median); it is not currently listed in the CISA KEV catalog.

The strongest mitigations our analysis identified map to SC-24 (Fail in Known State) and SI-17 (Fail-safe Procedures) — see the control section below for these in your framework.

Deeper analysis AI-assisted summary

Synthesised by an AI model from the NVD description and linked references — a reading aid, not an authoritative source.

CVE-2026-29643 is an improper exceptional-condition handling flaw (CWE-703) in the CSR subsystem, known as NewCSR, of XiangShan, an open-source high-performance RISC-V processor. The vulnerability affects commit edb1dfaf7d290ae99724594507dc46c2c2125384 dated 2024-11-28. In affected versions, specific sequences of CSR operations targeting non-existent or custom CSR addresses trigger an illegal-instruction exception but fail to reliably transfer control to the configured trap handler (mtvec), resulting in control-flow disruption that can leave the core in a hung or unrecoverable state.

A local attacker with the ability to execute code on the processor (AV:L/PR:L) can exploit this issue with low complexity and no user interaction required. Successful exploitation causes a denial of service by disrupting core operation and may lead to inconsistent architectural state, with high impacts on integrity (I:H) and availability (A:H) but no confidentiality impact (C:N). The CVSS v3.1 base score is 7.1 (AV:L/AC:L/PR:L/UI:N/S:U/C:N/I:H/A:H).

The issue is documented in XiangShan GitHub issue #3959, with a patch available in pull request #3966. Related RISC-V specifications are referenced in the privileged ISA documentation for machine mode (mtvec) and private CSRs.

OWASP Top 10 for Web (2025)

A10:2025 Mishandling of Exceptional Conditions

EU & UK References

Vulnerability Data

XiangShan (Open-source high-performance RISC-V processor) commit edb1dfaf7d290ae99724594507dc46c2c2125384 (2024-11-28) contains an improper exceptional-condition handling flaw in its CSR subsystem (NewCSR). On affected versions, certain sequences of CSR operations targeting non-existent/custom CSR addresses may trigger an illegal-instruction exception but fail to reliably…

more

transfer control to the configured trap handler (mtvec), causing control-flow disruption and potentially leaving the core in a hung or unrecoverable state. This can be exploited by a local attacker able to execute code on the processor to cause a denial of service and potentially inconsistent architectural state.

CWE(s)
CWE-703

Related Threats

MITRE ATT&CK Enterprise Techniques

T1499 Endpoint Denial of Service Impact
Adversaries may perform Endpoint Denial of Service (DoS) attacks to degrade or block the availability of services to users.
attack.mitre.org →
T1499.004 Application or System Exploitation Impact
Adversaries may exploit software vulnerabilities that can cause an application or system to crash and deny availability to users.
attack.mitre.org →
T1068 Exploitation for Privilege Escalation Privilege Escalation
Adversaries may exploit software vulnerabilities in an attempt to elevate privileges.
attack.mitre.org →
T1190 Exploit Public-Facing Application Initial Access
Adversaries may attempt to exploit a weakness in an Internet-facing host or system to initially access a network.
attack.mitre.org →
T1203 Exploitation for Client Execution Execution
Adversaries may exploit software vulnerabilities in client applications to execute code.
attack.mitre.org →
T1210 Exploitation of Remote Services Lateral Movement
Adversaries may exploit remote services to gain unauthorized access to internal systems once inside of a network.
attack.mitre.org →
Derived from this CVE’s CWE(s) via the direct CWE→ATT&CK cross-walk.

CVEs Like This One

CVE-2025-68135Shared CWE-703
CVE-2024-0092Shared CWE-703
CVE-2023-0004Shared CWE-703
CVE-2024-38482Shared CWE-703
CVE-2026-56338Shared CWE-703
CVE-2026-28407Shared CWE-703
CVE-2024-29205Shared CWE-703
CVE-2025-13022Shared CWE-703
CVE-2025-58758Shared CWE-703
CVE-2025-59787Shared CWE-703

Affected Assets

Riscv
—
inferred from references and description; NVD did not file a CPE for this CVE

Mitigating Controls

Mitigating Controls (NIST 800-53 r5) AI

SC-24 Fail in Known State good match

Enforces failure to a known state while preserving required properties, limiting impact of unhandled exceptions.

SI-17 Fail-safe Procedures good match

Mandates explicit fail-safe procedures triggered by indicated failures, structurally preventing unhandled exceptional conditions.

SA-8 Security and Privacy Engineering Principles partial match

Requires application of security engineering principles that include robust exception and error handling during design.

SI-11 Error Handling partial match

Requires generation of safe, actionable error messages that directly addresses proper handling of exceptional conditions.

Mitigating Controls (NIST CSF 2.0) AI

Derived directly from the weakness types (CWEs) cited in the NVD entry via our AI-authored CWE→CSF cross-walk (authority under review) — links open the control.

PR.PS-06 mostly match
prevents

Secure SDLC practices explicitly require anticipating and correctly handling exceptional conditions during design and coding.

Mitigating Controls (ISO/IEC 27001:2022 Annex A) AI

Derived directly from the weakness types (CWEs) cited in the NVD entry via our AI-authored CWE→ISO cross-walk (authority under review) — links open the control.

A.6.8 Information security event reporting none match
none

Reporting of unhandled errors or exceptional conditions surfaces latent failure paths so they can be corrected before exploitation.

References