CVE-2023-20599
Raw vector
CVSS:3.1/AV:L/AC:L/PR:H/UI:N/S:C/C:H/I:H/A:NSummary
CVE-2023-20599 is a high-severity Improper Access Control for Register Interface (CWE-1262) vulnerability in Amd (inferred from references). Its CVSS base score is 7.9 (High).
Operationally, exploitation aligns with the MITRE ATT&CK technique Firmware Corruption (T1495); ranked at the 5th percentile by exploit likelihood (below the median); it is not currently listed in the CISA KEV catalog.
The strongest mitigations our analysis identified map to AC-3 (Access Enforcement) and AC-6 (Least Privilege) — see the control section below for these in your framework.
EU & UK References
- 🇪🇺 ENISA EUVD: EUVD-2023-24778
Vulnerability Data
Improper register access control in ASP may allow a privileged attacker to perform unauthorized access to ASP’s Crypto Co-Processor (CCP) registers from x86 resulting in potential loss of control of cryptographic key pointer/index leading to loss of integrity or confidentiality.
- CWE(s)
Related Threats
MITRE ATT&CK Enterprise Techniques
CVEs Like This One
Affected Assets
Mitigating Controls
Mitigating Controls (NIST 800-53 r5) AI
Enforcing approved authorizations for logical access directly stops unauthorized software from reaching memory-mapped registers.
Least-privilege assignment restricts which processes may access hardware registers, reducing the chance of improper interface exposure.
Mitigating Controls (NIST CSF 2.0) AI
Derived directly from the weakness types (CWEs) cited in the NVD entry via our AI-authored CWE→CSF cross-walk (authority under review) — links open the control.
Mitigating Controls (ISO/IEC 27001:2022 Annex A) AI
Derived directly from the weakness types (CWEs) cited in the NVD entry via our AI-authored CWE→ISO cross-walk (authority under review) — links open the control.
Security testing can discover improper register access but does not prevent it at runtime.
Privileged utility programs may touch registers, so the control partially mitigates misuse.
Privileged access rights directly restrict who can read/write hardware registers.
Secure architecture principles require proper hardware register access controls by design.
Secure coding practices prevent unauthorized register access in firmware and drivers.
Information access restriction explicitly limits software access to memory-mapped register interfaces.