Cyber Resilience

CWE · MITRE source

CWE-1262Improper Access Control for Register Interface

Abstraction: Base · CVEs in our corpus: 11

The product uses memory-mapped I/O registers that act as an interface to hardware functionality from software, but there is improper access control to those registers.

Software commonly accesses peripherals in a System-on-Chip (SoC) or other device through a memory-mapped register interface. Malicious software could tamper with any security-critical hardware data that is accessible directly or indirectly through the register interface, which could lead to a loss of confidentiality and integrity.

Last updated: 04 July 2026 00:28 UTC

Cumulative inbound coverage

How completely the frameworks we cross-walk collectively cover this — the verdict is the strongest single mapping (overlapping partials are not summed); breadth shows the corroboration behind it.

Collective: mostly · 3 mapping(s) from 2 framework(s): ATT&CK 2 (partial) · CAPEC 1 (mostly)

See the full cumulative-coverage rollup →

NIST 800-53 r5 controls that address this weakness (0)AI

Control Title Family Why it addresses this CWE
No NIST controls proposed yet.

MITRE ATT&CK techniques this weakness enables

Our own two-way CWE↔ATT&CK cross-walk — a direct mapping with no public source (the CWE→CAPEC→ATT&CK chain leaves most top weaknesses, incl. XSS and SQLi, mapped to nothing). Drafted by Grok and spot-checked by Claude Opus 4.8.

Direction: other covers this; this covers other (F/M/P = full / mostly / partial).

Top CVEs of this weakness type, ranked by Risk Priority

CVE Risk CVSS EPSS Published
CVE-2015-83255.57.80.00632016-05-01
CVE-2022-230055.58.70.00822023-01-23
CVE-2024-63545.57.20.00792024-06-26
CVE-2023-205995.57.90.00162025-06-10
CVE-2025-473855.57.80.00072026-03-02
CVE-2025-18823.55.00.00202025-03-03
CVE-2024-574923.55.50.00182025-03-10
CVE-2024-455563.56.50.00082025-04-07
CVE-2025-207883.54.40.00062025-12-02
CVE-2025-361941.52.80.00112026-02-02