Cyber Resilience

CVE-2025-54509

Published
09 June 2026
Modified
23 July 2026
CVSS Score v4 4.0
Click a component to see what it means
Raw vectorCVSS:4.0/AV:L/AC:L/AT:P/PR:H/UI:N/VC:N/VI:N/VA:N/SC:N/SI:H/SA:N/E:X/CR:X/IR:X/AR:X/MAV:X/MAC:X/MAT:X/MPR:X/MUI:X/MVC:X/MVI:X/MVA:X/MSC:X/MSI:X/MSA:X/S:X/AU:X/R:X/V:X/RE:X/U:X
EPSS Score 0.0013 3th percentile
Risk Priority 17 floored blend · peak EPSS

Summary

CVE-2025-54509 is a medium-severity Improper Access Control for Register Interface (CWE-1262) vulnerability in Amd (inferred from references). Its CVSS base score is 4.0 (Medium).

Operationally, exploitation aligns with the MITRE ATT&CK technique Firmware Corruption (T1495); ranked at the 3th percentile by exploit likelihood (below the median); it is not currently listed in the CISA KEV catalog.

The strongest mitigations our analysis identified map to AC-3 (Access Enforcement) and AC-6 (Least Privilege) — see the control section below for these in your framework.

EU & UK References

Vulnerability Data

Improper access control for register interface in the Input-Output Memory Management Unit (IOMMU) could allow a privileged attacker to cause non-coherent accesses by the AMD Secure Processor (ASP), potentially resulting in loss of integrity.

CWE(s)
CWE-1262

Related Threats

MITRE ATT&CK Enterprise Techniques

T1495 Firmware Corruption Impact
Adversaries may overwrite or corrupt the flash memory contents of system BIOS or other firmware in devices attached to a system in order to render them inoperable or unable to boot, thus denying the availability to use the devices and/or…
attack.mitre.org →
T1542 Pre-OS Boot Stealth
Adversaries may abuse Pre-OS Boot mechanisms as a way to establish persistence on a system.
attack.mitre.org →
T1601 Modify System Image Defense Impairment
Adversaries may make changes to the operating system of embedded network devices to weaken defenses and provide new capabilities for themselves.
attack.mitre.org →
Derived from this CVE’s CWE(s) via the direct CWE→ATT&CK cross-walk.

CVEs Like This One

CVE-2023-20599Shared CWE-1262
CVE-2024-45556Shared CWE-1262
CVE-2025-36194Shared CWE-1262
CVE-2025-47385Shared CWE-1262
CVE-2024-6354Shared CWE-1262
CVE-2024-57492Shared CWE-1262
CVE-2025-1882Shared CWE-1262

Affected Assets

Amd
—
inferred from references and description; NVD did not file a CPE for this CVE

Mitigating Controls

Mitigating Controls (NIST 800-53 r5) AI

AC-3 Access Enforcement good match

Enforcing approved authorizations for logical access directly stops unauthorized software from reaching memory-mapped registers.

AC-6 Least Privilege good match

Least-privilege assignment restricts which processes may access hardware registers, reducing the chance of improper interface exposure.

Mitigating Controls (NIST CSF 2.0) AI

Derived directly from the weakness types (CWEs) cited in the NVD entry via our AI-authored CWE→CSF cross-walk (authority under review) — links open the control.

PR.AA-05 mostly match
prevents

Defining, enforcing, and reviewing access permissions and least privilege directly addresses unauthorized register access.

PR.IR-01 partial match
prevents

Protecting environments from unauthorized logical access can prevent improper register-interface usage.

Mitigating Controls (ISO/IEC 27001:2022 Annex A) AI

Derived directly from the weakness types (CWEs) cited in the NVD entry via our AI-authored CWE→ISO cross-walk (authority under review) — links open the control.

A.8.29 Security testing in development and acceptance mostly match
finds

Security testing can discover improper register access but does not prevent it at runtime.

A.8.18 Use of privileged utility programs partial match
mitigates

Privileged utility programs may touch registers, so the control partially mitigates misuse.

A.8.2 Privileged access rights partial match
prevents

Privileged access rights directly restrict who can read/write hardware registers.

A.8.27 Secure system architecture and engineering principles partial match
prevents

Secure architecture principles require proper hardware register access controls by design.

A.8.28 Secure coding partial match
prevents

Secure coding practices prevent unauthorized register access in firmware and drivers.

A.8.3 Information access restriction partial match
prevents

Information access restriction explicitly limits software access to memory-mapped register interfaces.

References