Cyber Resilience

CVE-2025-0647

Arm C1-Ultra Firmware

Published
14 January 2026
Modified
26 January 2026
Patch / advisory
CVSS Score v3.1 7.9
Click a component to see what it means
Raw vectorCVSS:3.1/AV:L/AC:L/PR:H/UI:N/S:C/C:H/I:H/A:N
EPSS Score 0.0015 5th percentile
Risk Priority 50 floored blend · peak EPSS

Summary

CVE-2025-0647 is a high-severity Sensitive Information in Resource Not Removed Before Reuse (CWE-226) vulnerability in Arm C1-Ultra Firmware. Its CVSS base score is 7.9 (High).

Operationally, exploitation aligns with the MITRE ATT&CK technique OS Credential Dumping (T1003); ranked at the 5th percentile by exploit likelihood (below the median); it is not currently listed in the CISA KEV catalog.

The strongest mitigations our analysis identified map to MP-6 (Media Sanitization) and SC-4 (Information in Shared System Resources) — see the control section below for these in your framework.

Deeper analysis AI-assisted summary

Synthesised by an AI model from the NVD description and linked references — a reading aid, not an authoritative source.

CVE-2025-0647 affects certain Arm CPUs, where a CPP RCTX instruction executed on one Processing Element (PE) may inhibit TLB invalidation when a TLBI instruction is issued to that PE, either by the same PE or another PE in the shareability domain. This results in the PE retaining stale TLB entries that should have been invalidated. The vulnerability is rated with a CVSS v3.1 base score of 7.9 (AV:L/AC:L/PR:H/UI:N/S:C/C:H/I:H/A:N) and is associated with CWE-226 (Sensitive Information in Resource Not Removed Before Reuse).

A local attacker with high privileges can exploit this vulnerability with low complexity and no user interaction required. Successful exploitation allows high-impact confidentiality and integrity violations, such as unauthorized access to sensitive data or modification of memory mappings, due to the retention of stale TLB entries, with a changed scope that elevates the attack surface.

Mitigation details are available in the Arm developer documentation at https://developer.arm.com/documentation/111546, along with additional analysis at https://graph.volerion.com/view?ID=CVE-2025-0647. The vulnerability was published on 2026-01-14T11:15:50.027.

EU & UK References

Vulnerability Data

In certain Arm CPUs, a CPP RCTX instruction executed on one Processing Element (PE) may inhibit TLB invalidation when a TLBI is issued to the PE, either by the same PE or another PE in the shareability domain. In this…

more

case, the PE may retain stale TLB entries which should have been invalidated by the TLBI.

CWE(s)

Related Threats

MITRE ATT&CK Enterprise Techniques

T1003 OS Credential Dumping Credential Access
Adversaries may attempt to dump credentials to obtain account login and credential material, normally in the form of a hash or a clear text password.
T1552 Unsecured Credentials Credential Access
Adversaries may search compromised systems to find and obtain insecurely stored credentials.
T1552.001 Credentials In Files Credential Access
Adversaries may search local file systems and remote file shares for files containing insecurely stored credentials.
T1552.002 Credentials in Registry Credential Access
Adversaries may search the Registry on compromised systems for insecurely stored credentials.
T1552.004 Private Keys Credential Access
Adversaries may search for private key certificate files on compromised systems for insecurely stored credentials.
T1003.001 LSASS Memory Credential Access
Adversaries may attempt to access credential material stored in the process memory of the Local Security Authority Subsystem Service (LSASS).
Derived from this CVE’s CWE(s) via the direct CWE→ATT&CK cross-walk.

CVEs Like This One

CVE-2024-7883Same vendor: Arm
CVE-2024-7881Same product: Arm C1-Premium
CVE-2024-5660Same product: Arm Cortex-A710
CVE-2019-25560Shared CWE-226
CVE-2025-14858Shared CWE-226
CVE-2024-21850Shared CWE-226
CVE-2025-2522Shared CWE-226
CVE-2025-13108Shared CWE-226
CVE-2026-32960Shared CWE-226
CVE-2025-11602Shared CWE-226

Affected Assets

arm
c1-ultra firmware
all versions
arm
c1-premium firmware
all versions
arm
cortex-a710 firmware
all versions
arm
cortex-x2 firmware
all versions
arm
cortex-x3 firmware
all versions
arm
cortex-x4 firmware
all versions
arm
cortex-x925 firmware
all versions
arm
neoverse-v2 firmware
all versions
arm
neoverse-v3 firmware
all versions
arm
neoverse-v3ae firmware
all versions
+1 more product configuration(s) — see NVD for full list

Mitigating Controls

Control response

Prevent
Stop it (NIST 800-53)

Detect
Catch it (NIST detect / respond)

Harden
Shrink the surface (DISA STIG)
  • 4 hardening rules · 4 OS baselines
Validate
Prove the fix (OWASP ASVS)
  • V14.2.8
  • V14.3.1

Mitigating Controls (NIST 800-53 r5) AI

MP-6 requires sanitization of media before release for reuse, directly stopping sensitive data from remaining in resources made available to others.

SC-4 requires preventing unintended information transfer through shared system resources such as memory, which is achieved by clearing data before reuse.

Mitigating Controls (NIST CSF 2.0) AI

Derived directly from the weakness types (CWEs) cited in the NVD entry via our AI-authored CWE→CSF cross-walk (authority under review) — links open the control.

PR.DS-10 full match
prevents

Explicit example calls for removing confidential data (e.g., from process memory) after use, directly preventing reuse of uncleared resources.

Mitigating Controls (ISO/IEC 27001:2022 Annex A) AI

Derived directly from the weakness types (CWEs) cited in the NVD entry via our AI-authored CWE→ISO cross-walk (authority under review) — links open the control.

degrades

Explicitly requires secure deletion of information before resources are reused or disposed.

prevents

Mandates secure disposal or re-use of equipment, covering media sanitization but not in-memory reuse.

finds

Security testing can detect failures to sanitize resources before reuse.

prevents

Secure SDLC includes requirements for clearing sensitive data during resource lifecycle transitions.

prevents

Secure coding practices can prevent leaving sensitive data in memory or files before reuse.

Hardening callouts derived

Configuration rules from DISA STIG baselines that bear on weaknesses of the type cited by this CVE. Each rule is shown with the relationship its mapping actually records, against the CWE it was authored against. Derived via CVE→CWE over `controls_xwalks` (authoritative rows only; rows rated `none` are excluded).

Oracle Linux 8 (1 rule)
  • V-248579 OL 8 must restrict access to the kernel message buffer. prevents CWE-226
Oracle Linux 9 (1 rule)
  • V-271745 OL 9 must restrict access to the kernel message buffer. prevents CWE-226
RHEL 8 (1 rule)
  • V-230269 RHEL 8 must restrict access to the kernel message buffer. prevents CWE-226
RHEL 9 (1 rule)
  • V-257797 RHEL 9 must restrict access to the kernel message buffer. prevents CWE-226

References