Cyber Resilience

CVE-2025-14857

Published
07 April 2026
Modified
24 July 2026
CVSS Score v4 5.4
Click a component to see what it means
Raw vectorCVSS:4.0/AV:P/AC:L/AT:P/PR:N/UI:N/VC:H/VI:H/VA:H/SC:L/SI:L/SA:N/E:X/CR:X/IR:X/AR:X/MAV:X/MAC:X/MAT:X/MPR:X/MUI:X/MVC:X/MVI:X/MVA:X/MSC:X/MSI:X/MSA:X/S:X/AU:N/R:A/V:D/RE:M/U:X
EPSS Score 0.0024 16th percentile
Risk Priority 22 floored blend · peak EPSS

Summary

CVE-2025-14857 is a medium-severity Write-what-where Condition (CWE-123) vulnerability in Semtech LoRa LR11xxx (inferred from references). Its CVSS base score is 5.4 (Medium).

Operationally, exploitation aligns with the MITRE ATT&CK technique Exploitation for Privilege Escalation (T1068); ranked at the 16th percentile by exploit likelihood (below the median); it is not currently listed in the CISA KEV catalog.

The strongest mitigations our analysis identified map to SI-16 (Memory Protection) and SA-8 (Security and Privacy Engineering Principles) — see the control section below for these in your framework.

EU & UK References

Vulnerability Data

An improper access control vulnerability exists in Semtech LoRa LR11xxx transceivers running early versions of firmware where the memory write command accessible via the physical SPI interface fails to enforce write protection on the program call stack. An attacker with…

more

physical access to the SPI interface can overwrite stack memory to hijack program control flow and achieve limited arbitrary code execution. However, the impact is limited to the active attack session: the device's secure boot mechanism prevents persistent firmware modification, the crypto engine isolates cryptographic keys from direct firmware access, and all modifications are lost upon device reboot or loss of physical access.

CWE(s)
CWE-123

Related Threats

MITRE ATT&CK Enterprise Techniques

T1068 Exploitation for Privilege Escalation Privilege Escalation
Adversaries may exploit software vulnerabilities in an attempt to elevate privileges.
attack.mitre.org →
T1190 Exploit Public-Facing Application Initial Access
Adversaries may attempt to exploit a weakness in an Internet-facing host or system to initially access a network.
attack.mitre.org →
T1203 Exploitation for Client Execution Execution
Adversaries may exploit software vulnerabilities in client applications to execute code.
attack.mitre.org →
T1210 Exploitation of Remote Services Lateral Movement
Adversaries may exploit remote services to gain unauthorized access to internal systems once inside of a network.
attack.mitre.org →
T1212 Exploitation for Credential Access Credential Access
Adversaries may exploit software vulnerabilities in an attempt to collect credentials.
attack.mitre.org →
T1687 Exploitation for Defense Impairment Defense Impairment
Adversaries may exploit vulnerabilities in security software, infrastructure, or defensive components to degrade, disable, or otherwise continue to impair their ability to prevent, detect, or respond to malicious activity.
attack.mitre.org →
Derived from this CVE’s CWE(s) via the direct CWE→ATT&CK cross-walk.

CVEs Like This One

CVE-2024-36877Shared CWE-123
CVE-2026-30121Shared CWE-123
CVE-2025-9900Shared CWE-123
CVE-2024-45142Shared CWE-123
CVE-2025-69809Shared CWE-123
CVE-2025-7403Shared CWE-123
CVE-2026-45257Shared CWE-123
CVE-2024-2607Shared CWE-123
CVE-2025-29943Shared CWE-123
CVE-2026-43284Shared CWE-123

Affected Assets

Semtech
LoRa LR11xxx
inferred from references and description; NVD did not file a CPE for this CVE

Mitigating Controls

Control response

Prevent
Stop it (NIST 800-53)

—

Detect
Catch it (NIST detect / respond)

—

Harden
Shrink the surface (DISA STIG)
  • 4 hardening rules · 4 OS baselines
Validate
Prove the fix (OWASP ASVS)

—

Mitigating Controls (NIST 800-53 r5) AI

SI-16 Memory Protection good match

Memory-protection mechanisms block unauthorized writes to arbitrary locations even if a write-what-where primitive exists.

SA-8 Security and Privacy Engineering Principles partial match

Secure engineering principles require memory-safe coding and bounds checking that eliminate the root cause of write-what-where flaws.

SC-39 Process Isolation partial match

Process isolation confines the blast radius of an arbitrary write so it cannot affect other domains.

SI-10 Information Input Validation partial match

Input validation directly stops malformed data from triggering buffer overflows that produce arbitrary write-what-where conditions.

Mitigating Controls (NIST CSF 2.0) AI

Derived directly from the weakness types (CWEs) cited in the NVD entry via our AI-authored CWE→CSF cross-walk (authority under review) — links open the control.

PR.PS-06 mostly match
prevents

Secure SDLC practices directly prevent arbitrary write conditions via safe coding, bounds checking, and memory-safe constructs.

Mitigating Controls (ISO/IEC 27001:2022 Annex A) AI

Derived directly from the weakness types (CWEs) cited in the NVD entry via our AI-authored CWE→ISO cross-walk (authority under review) — links open the control.

A.8.29 Security testing in development and acceptance mostly match
finds

Security testing in development and acceptance can detect write-what-where conditions before deployment.

A.8.25 Secure development life cycle partial match
prevents

Secure development lifecycle practices directly reduce the likelihood of write-what-where flaws such as buffer overflows.

A.8.26 Application security requirements partial match
prevents

Application security requirements can mandate input validation and bounds checking that mitigate arbitrary write conditions.

A.8.27 Secure system architecture and engineering principles partial match
prevents

Secure architecture and engineering principles discourage unsafe memory handling that leads to write-what-where vulnerabilities.

A.8.28 Secure coding partial match
prevents

Secure coding standards explicitly forbid unsafe buffer operations that enable arbitrary memory writes.

A.8.32 Change management partial match
prevents

Change management processes help ensure security fixes for such weaknesses are properly deployed.

Hardening callouts derived

Configuration rules from DISA STIG baselines that bear on weaknesses of the type cited by this CVE. Each rule is shown with the relationship its mapping actually records, against the CWE it was authored against. Derived via CVE→CWE over `controls_xwalks` (authoritative rows only; rows rated `none` are excluded).

Oracle Linux 8 (1 rule)
  • V-248592 OL 8 must clear memory when it is freed to prevent use-after-free attacks. prevents CWE-123
RHEL 8 (1 rule)
  • V-230279 RHEL 8 must clear memory when it is freed to prevent use-after-free attacks. prevents CWE-123
Windows 10 (1 rule)
  • V-220727 Structured Exception Handling Overwrite Protection (SEHOP) must be enabled. prevents CWE-123
Windows 11 (1 rule)
  • V-253284 Structured Exception Handling Overwrite Protection (SEHOP) must be enabled. prevents CWE-123

References