Cyber Resilience

CVE-2025-0012

Published
10 February 2026
Modified
15 April 2026
CVSS Score v4 6.8
Click a component to see what it means
Raw vectorCVSS:4.0/AV:L/AC:L/AT:N/PR:H/UI:N/VC:L/VI:H/VA:N/SC:N/SI:N/SA:N/E:X/CR:X/IR:X/AR:X/MAV:X/MAC:X/MAT:X/MPR:X/MUI:X/MVC:X/MVI:X/MVA:X/MSC:X/MSI:X/MSA:X/S:X/AU:X/R:X/V:X/RE:X/U:X
EPSS Score 0.0014 3th percentile
Risk Priority 22 floored blend · peak EPSS

Summary

CVE-2025-0012 is a medium-severity Improper Handling of Overlap Between Protected Memory Ranges (CWE-1260) vulnerability in Amd (inferred from references). Its CVSS base score is 6.8 (Medium).

Operationally, exploitation aligns with the MITRE ATT&CK technique Process Injection (T1055); ranked at the 3th percentile by exploit likelihood (below the median); it is not currently listed in the CISA KEV catalog.

The strongest mitigations our analysis identified map to SC-39 (Process Isolation) and SI-16 (Memory Protection) — see the control section below for these in your framework.

EU & UK References

Vulnerability Data

Improper handling of overlap between the segmented reverse map table (RMP) and system management mode (SMM) memory could allow a privileged attacker corrupt or partially infer SMM memory resulting in loss of integrity or confidentiality.

CWE(s)
CWE-1260

Related Threats

MITRE ATT&CK Enterprise Techniques

T1055 Process Injection Stealth
Adversaries may inject code into processes in order to evade process-based defenses as well as possibly elevate privileges.
attack.mitre.org →
T1068 Exploitation for Privilege Escalation Privilege Escalation
Adversaries may exploit software vulnerabilities in an attempt to elevate privileges.
attack.mitre.org →
T1548 Abuse Elevation Control Mechanism Privilege Escalation
Adversaries may circumvent mechanisms designed to control privilege elevation to gain higher-level permissions.
attack.mitre.org →
T1611 Escape to Host Privilege Escalation
Adversaries may break out of a container or virtualized environment to gain access to the underlying host.
attack.mitre.org →
Derived from this CVE’s CWE(s) via the direct CWE→ATT&CK cross-walk.

CVEs Like This One

CVE-2025-29948Shared CWE-1260
CVE-2024-4778Shared CWE-1260
CVE-2025-1937Shared CWE-1260
CVE-2025-22889Shared CWE-1260

Affected Assets

Amd
—
inferred from references and description; NVD did not file a CPE for this CVE

Mitigating Controls

Mitigating Controls (NIST 800-53 r5) AI

SC-39 Process Isolation good match

Process isolation depends on correct non-overlapping memory protection domains.

SI-16 Memory Protection good match

Memory protection mechanisms must correctly handle ranges to block unauthorized execution or access.

AC-3 Access Enforcement partial match

Access enforcement directly stops bypass of memory protections that overlapping ranges would enable.

SC-3 Security Function Isolation partial match

Isolating security functions requires non-overlapping protected memory ranges to avoid bypass.

Mitigating Controls (NIST CSF 2.0) AI

Derived directly from the weakness types (CWEs) cited in the NVD entry via our AI-authored CWE→CSF cross-walk (authority under review) — links open the control.

PR.PS-06 mostly match
prevents

Secure development practices directly prevent flawed memory-range overlap logic in kernels and hypervisors.

ID.RA-01 partial match
prevents

Vulnerability identification can surface overlap defects after they are introduced but does not stop them at design time.

PR.AA-05 partial match
prevents

Enforcing access-control policy can include memory-range permissions, yet the weakness is an implementation flaw inside that enforcement.

Mitigating Controls (ISO/IEC 27001:2022 Annex A) AI

Derived directly from the weakness types (CWEs) cited in the NVD entry via our AI-authored CWE→ISO cross-walk (authority under review) — links open the control.

A.8.29 Security testing in development and acceptance mostly match
finds

Security testing in development and acceptance can detect overlap issues but does not itself prevent them.

A.8.27 Secure system architecture and engineering principles partial match
prevents

Secure system architecture and engineering principles require explicit memory-range separation and protection mechanisms that directly prevent overlapping protected regions.

A.8.28 Secure coding partial match
prevents

Secure coding standards mandate checks for address-range overlap and proper memory-protection configuration, mitigating the weakness at implementation time.

A.8.3 Information access restriction partial match
mitigates

Information access restriction policies rely on correct memory protection; eliminating overlap strengthens enforcement but does not define the policy.

References