Cyber Resilience

CVE-2025-22853

Published
12 August 2025
Modified
17 June 2026
CVSS Score v4 1.8
Click a component to see what it means
Raw vectorCVSS:4.0/AV:L/AC:L/AT:P/PR:H/UI:N/VC:N/VI:N/VA:N/SC:N/SI:L/SA:N/E:X/CR:X/IR:X/AR:X/MAV:X/MAC:X/MAT:X/MPR:X/MUI:X/MVC:X/MVI:X/MVA:X/MSC:X/MSI:X/MSA:X/S:X/AU:X/R:X/V:X/RE:X/U:X
EPSS Score 0.0015 5th percentile
Risk Priority 14 floored blend · peak EPSS

Summary

CVE-2025-22853 is a low-severity Improper Synchronization (CWE-662) vulnerability in Intel (inferred from references). Its CVSS base score is 1.8 (Low).

Operationally, exploitation aligns with the MITRE ATT&CK technique Exploitation for Privilege Escalation (T1068); ranked at the 5th percentile by exploit likelihood (below the median); it is not currently listed in the CISA KEV catalog.

The strongest mitigations our analysis identified map to SC-39 (Process Isolation) and SC-4 (Information in Shared System Resources) — see the control section below for these in your framework.

EU & UK References

Vulnerability Data

Improper synchronization in the firmware for some Intel(R) TDX may allow a privileged user to potentially enable escalation of privilege via local access.

CWE(s)
CWE-662

Related Threats

MITRE ATT&CK Enterprise Techniques

T1068 Exploitation for Privilege Escalation Privilege Escalation
Adversaries may exploit software vulnerabilities in an attempt to elevate privileges.
attack.mitre.org →
T1499.004 Application or System Exploitation Impact
Adversaries may exploit software vulnerabilities that can cause an application or system to crash and deny availability to users.
attack.mitre.org →
T1548 Abuse Elevation Control Mechanism Privilege Escalation
Adversaries may circumvent mechanisms designed to control privilege elevation to gain higher-level permissions.
attack.mitre.org →
Derived from this CVE’s CWE(s) via the direct CWE→ATT&CK cross-walk.

CVEs Like This One

CVE-2024-7409Shared CWE-662
CVE-2025-27104Shared CWE-662
CVE-2024-32644Shared CWE-662
CVE-2023-5088Shared CWE-662
CVE-2026-13489Shared CWE-662
CVE-2024-58131Shared CWE-662
CVE-2026-53277Shared CWE-662
CVE-2024-30387Shared CWE-662
CVE-2023-2801Shared CWE-662
CVE-2023-45084Shared CWE-662

Affected Assets

Intel
—
inferred from references and description; NVD did not file a CPE for this CVE

Mitigating Controls

Control response

Prevent
Stop it (NIST 800-53)

—

Detect
Catch it (NIST detect / respond)

—

Harden
Shrink the surface (DISA STIG)

—

Validate
Prove the fix (OWASP ASVS)
  • V15.4.1
  • V6.5.1
  • V15.1.3
  • V15.4.2

Mitigating Controls (NIST 800-53 r5) AI

SC-39 Process Isolation partial match

Process isolation reduces the attack surface and blast radius of synchronization failures but does not itself implement the required synchronization.

SC-4 Information in Shared System Resources partial match

SC-4 directly requires preventing unintended information transfer through shared resources, which is achieved only by proper synchronization primitives for exclusive access.

Mitigating Controls (NIST CSF 2.0) AI

Derived directly from the weakness types (CWEs) cited in the NVD entry via our AI-authored CWE→CSF cross-walk (authority under review) — links open the control.

PR.PS-06 mostly match
prevents

Secure SDLC practices directly require synchronization mechanisms and concurrency testing to prevent race conditions.

Mitigating Controls (ISO/IEC 27001:2022 Annex A) AI

Derived directly from the weakness types (CWEs) cited in the NVD entry via our AI-authored CWE→ISO cross-walk (authority under review) — links open the control.

A.8.29 Security testing in development and acceptance mostly match
finds

Security testing can detect synchronization flaws but does not itself implement the required controls.

A.8.25 Secure development life cycle partial match
prevents

Secure development lifecycle requires concurrency controls and synchronization primitives to prevent race conditions.

A.8.27 Secure system architecture and engineering principles partial match
prevents

Secure system architecture principles include thread-safety and resource-locking mechanisms to avoid improper synchronization.

A.8.28 Secure coding partial match
prevents

Secure coding standards explicitly mandate proper use of locks, semaphores, and atomic operations to eliminate race conditions.

References