Raw vector
CVSS:3.1/AV:L/AC:L/PR:N/UI:R/S:U/C:L/I:L/A:HSummary
CVE-2026-21493 is a medium-severity Reliance on Data/Memory Layout (CWE-188) vulnerability in Color Iccdev. Its CVSS base score is 6.6 (Medium).
Operationally, exploitation aligns with the MITRE ATT&CK technique Exploitation for Privilege Escalation (T1068); ranked at the 5th percentile by exploit likelihood (below the median); it is not currently listed in the CISA KEV catalog; a public proof-of-concept is referenced.
The strongest mitigations our analysis identified map to SA-11 (Developer Testing and Evaluation) and SC-24 (Fail in Known State) — see the control section below for these in your framework.
OWASP Top 10 for Web (2025)
EU & UK References
- 🇪🇺 ENISA EUVD: EUVD-2026-1156
Vulnerability Data
iccDEV provides a set of libraries and tools for working with ICC color management profiles. Versions 2.3.1.1 and below are vulnerable to Type Confusion in its CIccSingleSampledeCurveXml class during XML Curve Serialization. This issue is fixed in version 2.3.1.2.
- CWE(s)
Related Threats
MITRE ATT&CK Enterprise Techniques
CVEs Like This One
Affected Assets
Mitigating Controls
Control response
—
—
—
V1.5.2V3.2.3V15.3.5
Mitigating Controls (NIST 800-53 r5) AI
Developer testing and evaluation can discover incorrect layout assumptions through targeted test cases.
Enforces failure to a known state while preserving required properties, limiting impact of unhandled exceptions.
Mandates explicit fail-safe procedures triggered by indicated failures, structurally preventing unhandled exceptional conditions.
Engineering principles applied during design can explicitly disallow assumptions about memory or protocol layout.
Process isolation limits the blast radius when layout assumptions are violated but does not stop the flawed assumption itself.
Requires generation of safe, actionable error messages that directly addresses proper handling of exceptional conditions.
Mitigating Controls (NIST CSF 2.0) AI
Derived directly from the weakness types (CWEs) cited in the NVD entry via our AI-authored CWE→CSF cross-walk (authority under review) — links open the control.
Secure SDLC practices directly prevent invalid memory-layout assumptions via safe coding, reviews, and tooling.
Mitigating Controls (ISO/IEC 27001:2022 Annex A) AI
Derived directly from the weakness types (CWEs) cited in the NVD entry via our AI-authored CWE→ISO cross-walk (authority under review) — links open the control.
Security testing in development can detect layout-related defects before release.
Secure development lifecycle includes architecture and design reviews that can catch invalid memory-layout assumptions.
Application security requirements can mandate explicit data-structure and protocol-layout specifications.
Secure system architecture and engineering principles directly address assumptions about memory and protocol layout.
Secure coding standards and reviews target unsafe reliance on implicit data layout.
Reporting of unhandled errors or exceptional conditions surfaces latent failure paths so they can be corrected before exploitation.