Raw vector
CVSS:3.1/AV:L/AC:L/PR:L/UI:N/S:U/C:H/I:H/A:HSummary
CVE-2026-45916 is a high-severity Use After Free (CWE-416) vulnerability in Linux Linux Kernel. Its CVSS base score is 7.8 (High).
Operationally, exploitation aligns with the MITRE ATT&CK technique Exploitation for Privilege Escalation (T1068); ranked at the 6th percentile by exploit likelihood (below the median); it is not currently listed in the CISA KEV catalog.
The strongest mitigations our analysis identified map to SA-11 (Developer Testing and Evaluation) and SA-8 (Security and Privacy Engineering Principles) — see the control section below for these in your framework.
EU & UK References
- 🇪🇺 ENISA EUVD: EUVD-2026-32382
Vulnerability Data
In the Linux kernel, the following vulnerability has been resolved: power: supply: sbs-battery: Fix use-after-free in power_supply_changed() Using the `devm_` variant for requesting IRQ _before_ the `devm_` variant for allocating/registering the `power_supply` handle, means that the `power_supply` handle will be…
more
deallocated/unregistered _before_ the interrupt handler (since `devm_` naturally deallocates in reverse allocation order). This means that during removal, there is a race condition where an interrupt can fire just _after_ the `power_supply` handle has been freed, *but* just _before_ the corresponding unregistration of the IRQ handler has run. This will lead to the IRQ handler calling `power_supply_changed()` with a freed `power_supply` handle. Which usually crashes the system or otherwise silently corrupts the memory... Note that there is a similar situation which can also happen during `probe()`; the possibility of an interrupt firing _before_ registering the `power_supply` handle. This would then lead to the nasty situation of using the `power_supply` handle *uninitialized* in `power_supply_changed()`. Fix this racy use-after-free by making sure the IRQ is requested _after_ the registration of the `power_supply` handle. Keep the old behavior of just printing a warning in case of any failures during the IRQ request and finishing the probe successfully.
- CWE(s)
Related Threats
MITRE ATT&CK Enterprise TechniquesAI
Why these techniques?
Kernel UAF race in driver enables local memory corruption (potential priv esc via T1068) or system crash/DoS via T1499.004.
CVEs Like This One
Affected Assets
Mitigating Controls
Control response
- 3 hardening rules · 3 OS baselines
V1.4.3
Mitigating Controls (NIST 800-53 r5) AI
Developer testing and evaluation (including fuzzing, static analysis, and concurrency testing) directly catches use-after-free races from incorrect devm_ ordering before the flawed driver reaches production.
Security engineering principles require correct initialization ordering and resource lifetime management, eliminating the probe/remove race that allows power_supply_changed to be called on a freed object.
Memory protection mechanisms (guard pages, pointer poisoning, or allocator hardening) raise the bar for reliable exploitation of the use-after-free once the race window is hit.
Mitigating Controls (NIST CSF 2.0) AI
Derived directly from the weakness types (CWEs) cited in the NVD entry via our AI-authored CWE→CSF cross-walk (authority under review) — links open the control.
Secure SDLC practices directly incorporate memory-safety tooling and reviews that prevent most use-after-free defects.
Vulnerability identification processes can discover use-after-free issues via scanning or analysis but do not prevent their introduction.
Routine patching removes known use-after-free instances after they have been introduced in released software.
Mitigating Controls (ISO/IEC 27001:2022 Annex A) AI
Derived directly from the weakness types (CWEs) cited in the NVD entry via our AI-authored CWE→ISO cross-walk (authority under review) — links open the control.
Security testing in development can detect use-after-free bugs before release.
Secure SDLC mandates memory-safety practices that reduce use-after-free defects.
Application security requirements can specify memory-management rules that mitigate use-after-free.
Secure architecture principles include memory-safety design choices that limit use-after-free exposure.
Secure coding standards directly prescribe avoidance of use-after-free patterns.
Change-management processes help ensure memory-safety fixes are deployed consistently.