Cyber Resilience

CVE-2026-46181

Race Condition in Linux Kernel 4.9 – 6.18.30

Published
28 May 2026
Modified
20 July 2026
Patch / advisory
CVSS Score v3.1 7.8
Click a component to see what it means
Raw vectorCVSS:3.1/AV:L/AC:L/PR:L/UI:N/S:U/C:H/I:H/A:H
EPSS Score 0.0011 2th percentile
Risk Priority 54 floored blend · peak EPSS

Summary

CVE-2026-46181 is a high-severity Race Condition within a Thread (CWE-366) vulnerability in Linux Linux Kernel. Its CVSS base score is 7.8 (High).

Operationally, exploitation aligns with the MITRE ATT&CK technique Exploitation for Privilege Escalation (T1068); ranked at the 2th percentile by exploit likelihood (below the median); it is not currently listed in the CISA KEV catalog.

The strongest mitigations our analysis identified map to SA-11 (Developer Testing and Evaluation) and SA-15 (Development Process, Standards, and Tools) — see the control section below for these in your framework.

EU & UK References

Vulnerability Data

In the Linux kernel, the following vulnerability has been resolved: RDMA/mlx4: Fix mis-use of RCU in mlx4_srq_event() Sashiko points out the radix_tree itself is RCU safe, but nothing ever frees the mlx4_srq struct with RCU, and it isn't even accessed…

more

within the RCU critical section. It also will crash if an event is delivered before the srq object is finished initializing. Use the spinlock since it isn't easy to make RCU work, use refcount_inc_not_zero() to protect against partially initialized objects, and order the refcount_set() to be after the srq is fully initialized.

CWE(s)

Related Threats

MITRE ATT&CK Enterprise Techniques

T1068 Exploitation for Privilege Escalation Privilege Escalation
Adversaries may exploit software vulnerabilities in an attempt to elevate privileges.
T1548 Abuse Elevation Control Mechanism Privilege Escalation
Adversaries may circumvent mechanisms designed to control privilege elevation to gain higher-level permissions.
Derived from this CVE’s CWE(s) via the direct CWE→ATT&CK cross-walk.

CVEs Like This One

CVE-2024-40969Same product: Linux Linux Kernel
CVE-2024-43863Same product: Linux Linux Kernel
CVE-2024-56743Same product: Linux Linux Kernel
CVE-2024-35997Same product: Linux Linux Kernel
CVE-2024-27404Same product: Linux Linux Kernel
CVE-2024-40953Same product: Linux Linux Kernel
CVE-2024-27005Same product: Linux Linux Kernel
CVE-2024-40972Same product: Linux Linux Kernel
CVE-2024-35999Same product: Linux Linux Kernel
CVE-2024-35786Same product: Linux Linux Kernel

Affected Assets

linux
linux kernel
7.1 · 4.9 — 6.18.30 · 6.19 — 7.0.7

Mitigating Controls

Control response

Prevent
Stop it (NIST 800-53)

Detect
Catch it (NIST detect / respond)

Harden
Shrink the surface (DISA STIG)

Validate
Prove the fix (OWASP ASVS)
  • V15.4.2
  • V15.4.3
  • V17.2.6

Mitigating Controls (NIST 800-53 r5) AI

Developer testing and evaluation can include concurrency and stress testing that finds race conditions after they have been coded.

Requiring documented development standards and tools can mandate use of safe concurrency patterns that avoid introducing races.

Security engineering principles include requirements for synchronization primitives and thread-safe design that stop race conditions from being introduced.

Mitigating Controls (NIST CSF 2.0) AI

Derived directly from the weakness types (CWEs) cited in the NVD entry via our AI-authored CWE→CSF cross-walk (authority under review) — links open the control.

PR.PS-06 mostly match
prevents

Secure SDLC practices directly require synchronization primitives and concurrency analysis that prevent intra-thread race conditions.

Mitigating Controls (ISO/IEC 27001:2022 Annex A) AI

Derived directly from the weakness types (CWEs) cited in the NVD entry via our AI-authored CWE→ISO cross-walk (authority under review) — links open the control.

finds

Security testing can detect race conditions through concurrency and stress testing.

prevents

Secure development lifecycle includes concurrency and synchronization practices that reduce race conditions.

prevents

Application security requirements can mandate thread-safety and locking controls.

prevents

Secure architecture principles address concurrent access and resource synchronization.

prevents

Secure coding standards directly require proper synchronization primitives to prevent race conditions.

none

Change management can introduce or remove synchronization flaws during updates.

References